1. Field of the Invention
The present invention relates generally to an apparatus and a method for driving a sense amplifier circuit employed in a dynamic random access memory or the like, and more particularly, to an improvement of the amplification factor of the sense amplifier circuit.
2. Description of the Prior Art
FIG. 1 is a diagram showing a schematic structure of the whole of a data-reading portion of a dynamic random access memory to which the present invention will be applied. In FIG. 1, the dynamic random access memory comprises a memory cell array MA having memory cells for storing information arranged in a plurality of rows and columns, an address buffer AB receiving an external address externally applied for generating an internal address, an X decoder ADX for decoding the internal address from the address buffer AB to select a corresponding row in the memory cell array, a Y decoder ADY for decoding the internal column address from the address buffer AB to select a corresponding column or columns in the memory cell array, a (sense amplifier and I/O) block SI for detecting and amplifying information stored in the selected memory cell in the memory cell array MA and transmitting the same to an output buffer OB in response to a signal from the Y decoder ADY, and the output buffer OB receiving read-out data from the (sense amplifier and I/O) block SI for transmitting output data Dout to an exterior. In addition, there is provided as a peripheral circuit a control signal generating system CG for generating control signals for controlling timing of various operations of the dynamic random access memory. The details of each of the control signals generated by the control signal generating system CG will be described below.
FIG. 2 is a diagram showing a schematic structure of the memory cell array portion shown in FIG. 1. In FIG. 2, a memory cell array MA comprises a plurality of word lines WL1, WL2, . . . , WLn and a plurality of bit lines BL0, BL0, BL1, BL1, . . . , BLm, BLm. One row of memory cells is connected to one of the word lines WL1, . . . , WLn. The bit lines constitute folded bit lines, so that two bit lines constitute one bit line pair. More specifically, the bit lines BL0 and BL0 constitute one bit line pair, and the bit lines BL1 and BL1 constitute bit line pair. In the same manner, the bit lines BLn and BLn constitute one bit line pair. A memory cell 1 is disposed at an intersection of each of the bit lines BL0, BL0, . . . , BLm, BLm and every other word line. More specifically, in each of the bit line pairs, a memory cell is located at an intersection of one word line and either one bit line of the bit line pair. There is provided for each of one bit line pairs a precharging/equalizing circuit 150 for equalizing potentials on each of the bit line pairs and precharging the bit line pair to a predetermined potential V.sub.B. In addition, there is provided for each of the bit line pairs a sense amplifier 50 responsive to signals .phi.A and .phi.B transmitted onto signal lines 14 and 17 to be activated for detecting the potential difference between the bit line pair and differentially amplifying the same. Each of the bit lines is selectively connected to data input/output buses I/O and I/O in response to an address decoded signal from a Y decoder ADY. More specifically, the bit lines BL0 and BL0 are connected to the data input/output lines I/O and I/O through transfer gates TO and TO', respectively. In the same manner, the bit lines BL1 and BL1 are connected to the data input/output lines I/O and I/O through transfer gates T1 and T1l', respectively, and the bit lines BLm and BLm are connected to the data input/output lines I/O and I/O through the transfer gates Tm and Tm', respectively. The address decoded signal from the Y decoder ADY is transmitted to a gate of each of the transfer gates TO, TO', . . . , Tm, Tm'. Consequently, one bit line pair is connected to the data input/output lines I/O and I/O.
FIG. 3 is a diagram showing a detailed structure of one bit line pair out of the bit line pairs shown in FIG. 2 and a sense amplifier control circuit associated therewith. In FIG. 3, only one word line is shown to avoid the complexity of the drawing.
A precharging/equalizing circuit 150 for precharging one bit line pair 2 and 7 to a predetermined potential V.sub.B at a standby time as well as equalizing potentials on the bit lines 2 and 7 to the predetermined potential comprises an n channel insulated gate field effect transistor (referred to as MIS transistor hereinafter) responsive to a precharging signal .phi.P for transmitting the predetermined precharge potential V.sub.B to both the bit lines 2 and 7, and an n channel MIS transistor 12 responsive to an equalizing signal .phi.E applied through a signal line 13 for electrically connecting the bit lines 2 and 7 thereby to equalize the potentials on the bit lines 2 and 7. n channel MIS transistors 9 and 10 for precharging are rendered conductive in response to the precharging signal .phi.P applied through a signal line 11, to transmit the precharge potential V.sub.B transmitted onto a signal line 8 to the bit lines 2 and 7, respectively.
A sense amplifier 50 for differentially amplifying signals on the bit lines 2 and 7 comprises a pair of cross-coupled p channel MIS transistors 15 and 16 connected to the bit lines 2 and 7, respectively, and a pair of cross-coupled n channel MOS transistors 18 and 19 connected to the bit lines 2 and 7, respectively. The p channel MIS transistors 15 and 16 have their respective remaining electrodes connected together to a signal line 14, to receive a signal .phi.A. The n channel MOS transistors 18 and 19 have their respective remaining electrodes connected to a signal line 17 to receive a signal .phi.B on the signal line 17.
There is provided for the first sense amplifier driving signal line 14 a p channel MIS transistor 24 responsive to a control signal .phi.R for providing timing for activating a sense amplifier, to be rendered conductive for transmitting a power-supply potential Vcc onto the first sense amplifier driving signal line 14, an n channel MIS transistor 30 for keeping the first sense amplifier driving signal line 14 at a predetermined potential during a bit line precharging time period, and a constant voltage generating circuit 100.
There is provided for the second sense amplifier driving signal line 17 an n channel MIS transistor 27 responsive to a second control signal .phi.S for providing timing for activating a sense amplifier for connecting the second sense amplifier driving signal line 17 to a ground potential.
The p channel MIS transistor 24 for charging the first sense amplifier driving signal line 14 to the power-supply potential Vcc receives the sense amplifier activating signal .phi.R at its gate through a signal line 25 and the power-supply potential Vcc through a signal line 26 at one conduction terminal. The n channel MIS transistor 27 for discharging the second sense amplifier driving signal line 17 to the ground potential receives the second sense amplifier activating signal .phi.S through a signal line 28.
The constant voltage generating circuit 100 comprises a resistance 33 having its one terminal connected to the power-supply potential Vcc through the signal line 26, an n channel MIS transistor 35 of diode connection connected to the resistance 33 through a node 32, a p channel MIS transistor 36 of diode connection connected in series to the n channel MIS transistor 35 through a node 34, and an n channel MIS transistor 31 receiving a potential on the node 32 at its gate and at its one conduction terminal the power-supply potential Vcc through the signal line 26 for transmitting a predetermined potential to a node 29. The n channel MIS transistor 30 is responsive to a precharging signal .phi.P to be rendered conductive for transmitting a potential on the node 29 onto the first sense amplifier driving signal line 14.
The n channel MIS transistor 35 has its gate and drain connected to the node 32, and makes the potential on the node 32 higher, by a threshold voltage V.sub.TN of the transistor 35, than a potential on the node 34. The p channel MIS transistor 36 has both its gate and drain connected to a precharge potential V.sub.B through a signal line 8. Thus, a voltage higher, by the absolute value of a threshold voltage V.sub.TP of the transistor 36, than the precharge potential V.sub.B is applied to the node 34. The resistance 33 is provided for only supplying a voltage to the node 32, and has a large resistance value of several M.OMEGA. to several tens M.OMEGA.. In this structure, the potential on the node 32 becomes V.sub.B +.vertline.V.sub.TP .vertline.+V.sub.TN. The n channel MIS transistor 31 has a threshold voltage V.sub.TN, thereby to transmit a potential of V.sub.B +.vertline.V.sub.TP .vertline. to the node 29.
A memory cell 1 comprises a transfer gate 5 having its gate connected to a word line 3 and its source connected to the bit line 2, and a capacitance 6 connected to a drain of the transfer gate 5 through a node 4. Data in the memory cell 1 is stored in the node 4. That is, the node 4 is a so-called storage node.
At the time of selecting the word line 3, a word line driving signal Rn is transmitted on the selected word line, so that the transfer gate 5 formed of an n channel insulated gate field effect transistor is rendered conductive, whereby information stored in the memory cell 1 is transmitted onto the bit line 2. Although a memory cell connected to the bit line 7 is not shown, a memory cell is not provided at an intersection of the word line 3 and the bit line 7. Thus, in the structure shown in FIG. 3, when the memory cell 1 is selected, the bit line 7 provides a reference potential for the bit line 2.
The bit lines 2 and 7 have parasitic capacitances 20 and 21, respectively, and the first sense amplifier driving signal lines 14 and 17 have parasitic capacitances 22 and 23, respectively.
FIG. 4 is a waveform diagram for explaining an operation of the circuit structure shown in FIG. 3. FIG. 4 shows an operation to occur when data of logic "1" is stored in the memory cell 1 and information "1" stored in the memory cell 1 is read out. Since an operation continued from the preceding cycle must be explained in order to explain a data reading operation from the memory cell 1, FIG. 4 also shows a waveform diagram of the operation in the preceding cycle as well.
Referring now to FIGS. 3 and 4, description is made on an operation to occur when data of logic "1" stored in the memory cell 1 is read out.
It is assumed that in the preceding cycle, data is read out from a memory cell connected to the bit line 2 or 7, so that the potential on the bit line 2 is in a state of 0V and the potential on the bit line 7 is in a state of Vcc. This state is not exclusive. The reversed state is possible depending on data stored in the memory cell read out in the preceding cycle. After a level of a word line (not shown) which selected the memory cell in the preceding cycle becomes 0V, the sense amplifier driving signals .phi.S and .phi.R start to fall and rise at a time t0, respectively, so that the MIS transistors 27 and 24 are both rendered non-conductive, whereby the sense amplifier 50 is inactivated.
At a time t1, an equalizing signal .phi.E starts to rise, the equalizing MIS transistor 12 is rendered conductive. As a result, charges are moved from a bit line 7 at a high potential toward the bit line 2 at a low potential, so that the potentials on the bit lines 2 and 7 are both equalized to Vcc/2. Before the potential on each of the bit lines 2 and 7 becomes Vcc/2, conduction between the sense amplifier driving signal lines 14 and 17 is effected by the MIS transistors included in the sense amplifier 50, so that charges are moved from the sense amplifier driving signal line 14 at a high potential to the sense amplifier driving signal line 17 at a low potential. More specifically, a potential on the sense amplifier driving signal line 14 becomes in the potential Vcc/2+.vertline.V.sub.TP .vertline. which is higher, by the absolute value of the threshold voltage V.sub.TP of the MIS transistors 15 and 16, than the equalized potential Vcc/2 on the bit lines. On the other hand, a potential on the sense amplifier driving signal line 17 becomes Vcc/2-V.sub.TN which is lower, by the threshold voltage V.sub.TN of the MIS transistors 18 and 19, than the equalize potential Vcc/2 on the bit lines.
At a time t2, the precharging clock signal .phi.P rises from 0V in order to stabilize the potentials on the bit lines 2 and 7 at a Vcc/2 level, so that the precharging MIS transistors 9 and 10 are rendered conductive, whereby a power supply line 8 having a potential of Vcc/2 is connected to the bit lines 2 and 7. The precharge potential V.sub.B is set to one-half of an operating power-supply potential Vcc, i.e., Vcc/2.
At a time t3, the rise of the precharging clock signal .phi.P is terminated, so that the operation in the preceding cycle is terminated.
At a time t4, equalizing and charging of the bit lines 2 and 7 are terminated to complete the previous cycle, and then the current cycle is started. Consequently, both the bit line equalizing signal .phi.E and the precharging clock signal .phi.P start to fall, whereby the MIS transistors 9, 10 and 12 are rendered non-conductive.
At a time t5, the word line 3 is selected in response to the row address decoded signal from the X decoder. Consequently, the word line selecting signal Rn is transmitted onto the word line 3, whereby the potential on the word line 3 is raised. As a result, the MIS transistor 5 is rendered conductive so that charges stored in the capacitance 6 are moved toward the bit line 2, whereby the potential on the bit line 2 starts to be raised. The change in potential on the bit line 2 causes the MIS transistor 19 included in the sense amplifier 50 to be rendered conductive. As a result, the potentials on the bit line 7 and the sense amplifier driving signal lines 14 and 17 are changed, respectively. The details of the changes in potential on the bit line 7 and the sense amplifier driving signal lines 14 and 17 will be described below. The change in potential on the bit line 2 is very small (several 100s mV) and generally has a rising time constant of several 10ns.
At a time t6, the sense amplifier driving signal .phi.S rises, so that a very small difference in signal between the bit lines 2 and 7 is amplified by driving the sense amplifier 50. On this occasion, in order to stably operate the sense amplifier 50, it is desirable that an input signal thereof, i.e., the potential difference between the bit lines 2 and 7 is made as large as possible. In order to increase the potential difference between the bit lines 2 and 7, a time interval between the time t5 and the time t6 must be enlarged. However, in order to enhance the speed of reading out data stored in the memory cell, the time interval between the time t5 and the time t6 is generally set to a period between 15 and 25ns.
At a time t7, amplification of the potential difference in the signals by the sense amplifier 50 is terminated, so that the potential on the bit line 7 becomes a ground potential, whereby the potential difference is further increased.
Then, at the time t7, the bit line charging signal .phi.R also falls, so that the charging MIS transistor 24 is rendered conductive, whereby the potential on the sense amplifier driving signal line 14 is raised up to the power-supply potential Vcc. As a result, the bit line 2 is charged to the power-supply potential Vcc level through the MIS transistor 15 in the sense amplifier 50. Thus, a sensing operation performed by the sense amplifier 5 is completed. In this case, an operation triggered by the signal .phi.S and an operation triggered by the signal .phi.R may be distinguished from each other as a sensing operation and a restoring operation, respectively. However, in the following description, both operations are defined as a sensing operation.
After the potentials on the bit lines 2 and 7 are established to be the power-supply potential Vcc and the ground potential 0V, respectively, the bit lines 2 and 7 are connected to the data input/output lines I/O and I/O in response to an output of a Y decoder, respectively, so that data are read out.
Referring now to FIGS. 5 and 6, a very small change in potential at the time of reading out data on the bit line will be described in detail.
FIG. 5 is a diagram showing a potential after the movement of charges between a sense amplifier driving signal line and a bit line through a sense amplifier and the change in potential on each signal line.
FIG. 6 is a diagram showing the change in potential on each signal line at the time of reading out data in a memory cell.
It is assumed that data of logic "1" is read out from the memory cell 1. In this case, when the word line driving signal Rn applied to the word line 3 rises so that the potential level thereof exceeds Vcc/2+V.sub.TN, the MIS transistor 5 in the memory cell 1 starts to be rendered conductive, whereby the bit line 2 and the node 4 are connected to each other. Consequently, charges are moved from the node 4 toward the bit line 2, so that the potential on the bit line 2 is raised. Due to the rise in potential on the bit line 2, the MIS transistor 19 starts to be conductive, so that charges move from the bit line 7 toward the sense amplifier driving signal line 17. Consequently, the potential on the sense amplifier driving signal line 17 is raised and the potential on the bit line 7 is lowered. Due to the fall of the potential on the bit line 7, the MIS transistor 15 is rendered conductive, so that charges move from the sense amplifier driving signal line 14 toward the bit line 2. Consequently, the potential on the bit line 2 is raised. When the above described phenomenon is repeated, it would be considered that the potential on the bit line 2 is gradually raised. In practice, since the capacitance value of the parasitic capacitance 21 of the sense amplifier driving signal line 17 is smaller than the capacitance value of the parasitic capacitance 28 of the bit line 7, the potential on the sense amplifier driving signal line 17 is raised faster than the fall rate of the potential on the bit line 7. Consequently, the MIS transistor 19 is not easily rendered conductive, so that the rise of potential on the bit line 2 completes out at a relatively small value. In order to further raise the potential on the bit line 2, one approach may be considered that a capacitance is added to the sense amplifier driving signal line 17. However, in this approach, the discharging time constant of a discharge path from the bit line 7 is increased, so that the potential on the bit line 7 may not so lowered.
The above described phenomenon of the change in potential on the bit lines 2 and 7 is a transient phenomenon. The details thereof require analysis through calculation. Referring now to FIG. 5, description is made on the final state in which the movement of charges is stopped for the purpose of rough comparison with the structure in the present invention as described below.
As shown in FIG. 5, it is assumed that the changes in potential on the bit lines 2 and 7 after the movement of charges and the sense amplifier driving signal lines 14 and 17 are .DELTA.V+.DELTA.V2, .DELTA.V7, .DELTA.V14 and .DELTA.V17, respectively, where .DELTA.V denotes the amount of the shift in potential caused by reading out data of logic "1" from the memory cell 1. In addition, it is assumed that the capacitance values of the parasitic capacitances 20, 21, 27 and 28 are C20, C21, C27 and C28, respectively.
First, the case is considered where charges are moved between the bit line 2 and the sense amplifier driving signal line 14. In this case, from the conservation law of charges, the following equation is obtained: ##EQU1## That is, EQU C27.multidot..DELTA.V2=C20.multidot..DELTA.V14 (1)
Similarly, from the conservation law of charges between the bit line 7 and the sense amplifier driving signal line 17, the following equation is obtained: EQU C28.multidot..DELTA.V7=C21.multidot..DELTA.V17 (2)
Furthermore, the MIS transistor 19 is rendered non-conductive, so that the movement of charges to the sense amplifier driving signal line 17 is stopped. Thus, the following equation is obtained: EQU Vcc/2+.DELTA.V+.DELTA.V2-V.sub.TN =Vcc/2-V.sub.TN +.DELTA.V17
That is, EQU .DELTA.V+.DELTA.V2=.DELTA.V17 (3)
Similarly, the MIS transistor 15 is rendered non-conductive to stop the movement of charges to the bit line 2. Thus, the following equation is obtained: EQU Vcc/2-.DELTA.V7+.vertline.V.sub.TP .vertline. =Vcc/2+.vertline.V.sub.TP .vertline.-.DELTA.V14
That is, EQU .DELTA.V14ptm (4) EQU Substitution of the equation (4) into the equation (2) gives: EQU C28.multidot..DELTA.V14=C21.multidot..DELTA.V17 (5)
On the other hand, from the above described equation (1), the following equation is obtained: EQU .DELTA.V14=(C27/C20).multidot.V2 (6)
Substitution of the equation (6) into the equation (5) gives:
(C27.multidot.C28/C20).multidot..DELTA.V2=C21`.DELTA.V17
That is, EQU .DELTA.V17=(C27.multidot.C28/C20.multidot.C21).multidot..DELTA.V2 (7)
Substitution of the equation (7) into the equation (3) gives: EQU .DELTA.V={(C27.multidot.C28/C20.multidot.C21)-1}.multidot..DELTA.V2
That is, EQU .DELTA.V2=.DELTA.V/{(C27.multidot.C28/C20.multidot.C21)-1} (8)
Similarly, the following equations are obtained; ##EQU2##
Assuming that (C27=C28):(C20=C21)=10:1 and .DELTA.V.about.200 mV, the following values are obtained: EQU .DELTA.V2.apprxeq.200/99=2 mV, EQU .DELTA.V7=.DELTA.V14=1.1.times.200=220 mV, EQU .rarw.V17=100.multidot.200/99=202 mV
Using the above described values, the difference Vs in input potential applied to the sense amplifier 50 becomes as follows: ##EQU3## This value is a value obtained when the time interval between the time t5 and the time t6 in FIG. 4 is increased to infinity. The value must be actually set to a relatively short finite time (for example, 15 to 25 ns) in order to read out data from the memory cell at high speed.
On the other hand, a potential between adjacent bit lines is reduced to a value of about one-third to one-fourth of the above described value due to voltage noises caused by capacitive coupling between the bit lines as well as electrical imbalance between the bit lines which is inevitably associated with a practical manufacturing of the memory device, resulting in degradation of operating margin of the sense amplifier circuit. More specifically, it is desirable that the potential difference between input signals is made as large as possible in order to accurately operate the sense amplifier. However, the potential difference between the input signals to the sense amplifier is decreased as described above, so that the operating margin of the sense amplifier circuit is decreased, whereby a reliable sensing operation can not be performed.